Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors

This paper introduces a method for bounding the worst-case performance of programs running on multithreaded processors, such as the embedded cores found within network processors (NPs). Worst-case bounds can be useful in determining whether a given software implementation will provide stable (e.g., line rate) performance under all traffic conditions. Our method extends an approach from the real-time systems literature, namely the implicit path enumeration technique [7], and casts the problem of bounding worst-case performance as an integer linear programming problem. To evaluate the method, we model the Intel IXP 1200 microengines and compare worst-case estimates to a selection of results gathered via simulation of that NP architecture.